#ifndef T1_FSK_H_
#define T1_FSK_H_

#include "regs.h"
#include "iodef.h"

typedef struct {
        __IO uint32_t TXMD;     /* Transmit Mode Register */
        __IO uint32_t TXCTL;    /* Transmit Control Register */
        __IO uint32_t TXFSK;    /* Transmit FSK Parameter Register */
        __IO uint32_t TXDTMF;   /* Transmit DTMF Parameter Register */
        __IO uint32_t TXHFTW;   /* Transmit FSK HFTW Parameter Register */
        __IO uint32_t TXLFTW;   /* Transmit FSK LFTW Parameter Register */
        __IO uint32_t RXMD;     /* Receive Mode Register */
        __IO uint32_t RXFSK;    /* Receive FSK data Register */
        __IO uint32_t RXDTMF1;  /* Receive DTMF data1 Register */
        __IO uint32_t RXDTMF2;  /* Receive DTMF data2 Register */
        __IO uint32_t RXREG;    /* Receive FIFO data Register */
        __IO uint32_t GCTL;     /* Global Control Register */
        __IO uint32_t ISR;      /* Interrupt Status Register */
        __IO uint32_t IER;      /* Interrupt Enable Register */
        __IO uint32_t ICR;      /* Interrupt Clear Register */
        __IO uint32_t CSR;      /* Current Status Register */
        __IO uint32_t DTMFPT;   /* DTMF Present Time Register */
        __IO uint32_t DTMFAT;   /* DTMF Disappear Time Register */
        __IO uint32_t TXREG;    /* Transmit FIFO data Register */
        __IO uint32_t RXDB;     /* FSK/DTMF 2's Complement Register */
}fsk_reg_t;

/* TXMD */
#define TX_MODE_MSK             _MASK(0, 2)
#define TX_DIS                  _VALUE(0, 0)
#define TX_FSK_EN               _VALUE(0, 1)
#define TX_DTMF_EN              _VALUE(0, 2)
#define TX_FSK_DTMF_EN          _VALUE(0, 3)

/* TXCTL */
#define TX_START                _BIT(0)

/* TXFSK */
#define TX_MSB                  _BIT(12)
#define TX_FSK                  _BIT(11)

/* TXDTMF */
#define HDTX_CODE_MSK           _MASK(4, 3)
#define HDTX_CODE_1209HZ        _VALUE(4, 1)
#define HDTX_CODE_1336HZ        _VALUE(4, 2)
#define HDTX_CODE_1477HZ        _VALUE(4, 3)
#define HDTX_CODE_1633HZ        _VALUE(4, 4)
#define HDTX_CODE_2130HZ        _VALUE(4, 5)

#define LDTX_CODE_MSK           _MASK(0, 3)
#define LDTX_CODE_697HZ         _VALUE(4, 1)
#define LDTX_CODE_770HZ         _VALUE(4, 2)
#define LDTX_CODE_852HZ         _VALUE(4, 3)
#define LDTX_CODE_941HZ         _VALUE(4, 4)
#define LDTX_CODE_2750HZ        _VALUE(4, 5)
#define LDTX_CODE_450HZ         _VALUE(4, 6)

/* CSR */

#define DAC_FIFO_FULL		_BIT(6)
#define DAC_FIFO_EMPTY		_BIT(5)
#define DAC_FIFO_AVL		_BIT(4)
#define ADC_FIFO_FULL		_BIT(2)
#define ADC_FIFO_EMPTY		_BIT(1)
#define ADC_FIFO_AVL		_BIT(0)


/* FSK_GCTL */
#define GCTL_RXTXEN		_BIT(10)
#define GCTL_DAC_IN_SEL		_BIT(9)
#define GCTL_INT_EN		_BIT(8)

#define GCTL_DAC_TXMODE_MSK           _MASK(6, 2)
#define GCTL_DAC_TXMODE1	_VALUE(6, 0)
#define GCTL_DAC_TXMODE2	_VALUE(6, 1)

#define GCTL_ADC_RXMODE_MSK	_MASK(4, 2)
#define GCTL_ADC_RXMODE1	_VALUE(4, 0)
#define GCTL_ADC_RXMODE2	_VALUE(4, 1)

#define GCTL_DAC_TXFIFO_EN	_BIT(3)
#define GCTL_DAC_TXEN		_BIT(2)

#define GCTL_ADC_RXFIFO_EN	_BIT(1)
#define GCTL_ADC_RXEN		_BIT(0)


/*rxmd*/
#define RXMD_FSK_EN			(1u)
#define RXMD_DTMF_EN			(2u)
#define RXMD_FSK_DTMF_EN		(3u)	


/*ISR*/
#define ISR_DTMF_DATA_INTF		(1u<<9)
#define ISR_TXUERR_INTF			(1u<<8)
#define ISR_TX_FIFO_INTF		(1u<<7)
#define ISR_RXOERR_INTF			(1u<<6)
#define ISR_RX_FIFO_FULL_INTF	(1u<<5)
#define ISR_RX_FIFO_INTF		(1u<<4)
#define IER_RX_DTMF_DIS_INTF	(1u<<3)
#define IER_RX_DTMF_INTF		(1u<<2)
#define ISR_RX_FSK_INTF			(1u<<1)
#define ISR_TX_FSK_INTF			(1u)



/*IER*/
#define IER_DTMF_DATA_IEN		(1u<<9)
#define IER_TXUERR_IEN			(1u<<8)
#define IER_TX_FIFO_IEN			(1u<<7)
#define	IER_RXOERR_IEN			(1u<<6)
#define	IER_RX_FIFO_FULL_IEN	(1u<<5)
#define	IER_RX_FIFO_IEN			(1u<<4)
#define IER_RX_DTMF_DIS_IEN		(1u<<3)
#define IER_RX_DTMF_IEN			(1u<<2)
#define IER_RX_FSK_IEN			(1u<<1)
#define IER_TX_FSK_IEN			(1u)

/*ICR*/
#define ICR_DTMF_DATA_ICLR 		(1u<<9)
#define ICR_TXUERR_ICLR			(1u<<8)
#define ICR_TX_FIFO_ICL			(1u<<7)
#define	ICR_RXOERR_ICLR			(1u<<6)
#define	ICR_RX_FIFO_FULL_ICLR	(1u<<5)
#define	ICR_RX_FIFO_ICLR		(1u<<4)
#define ICR_RX_DTMF_DIS_ICLR	(1u<<3)	
#define ICR_RX_DTMF_ICLR		(1u<<2)
#define ICR_RX_FSK_ICLR			(1u<<1)
#define ICR_TX_FSK_ICLR			(1u)

/*txctl register description*/
#define TXCTL_TXSTAR_BUSY		(1u)
#define TXCTL_TXSTAR_IDLE		(0u)


/* TXHFTW */
#define FSK     ((fsk_reg_t *)T1_FSKDTMF_BASE)

typedef struct {
        __IO uint32_t ADC_IN_SEL;       /* ADC Input Select */
        __IO uint32_t ADC_REF_SEL;      /* ADC Reference Voltage Select */
        __IO uint32_t ADC_PWD_CTL;      /* ADC Power Down Control */
}adc_reg_t;


/* ADC_IN_SEL */
#define ADC_IN_SEL_MSAK		_MASK(0, 3)
#define ADC_IN_VBT	_VALUE(0, 0)
#define ADC_IN_VHS	_VALUE(0, 1)
#define ADC_IN_A2	_VALUE(0, 2)
#define ADC_IN_A3	_VALUE(0, 3)
#define ADC_IN_YM	_VALUE(0, 4)
#define ADC_IN_YP	_VALUE(0, 5)
#define ADC_IN_XM	_VALUE(0, 6)
#define ADC_IN_XP	_VALUE(0, 7)

/*ADC_REF_SEL */
#define ADC_REFH_MASK		_MASK(4, 2)
#define ADC_REFH_VREFH		_VALUE(4, 0)
#define ADC_REFH_YP		_VALUE(4, 1)
#define ADC_REFH_XP		_VALUE(4, 2)
#define ADC_REFH_AVDD33		_VALUE(4, 3)

#define ADC_REFL_MASK		_MASK(0, 2)
#define ADC_REFL_AGND33		_VALUE(0, 0)
#define ADC_REFL_YM		_VALUE(0, 1)
#define ADC_REFL_XM		_VALUE(0, 2)
//#define ADC_REFL_AGND33		_VALUE(0, 3)


/* ADC_PWD_CTL */
#define ADC_PWD_ON	(0u)
#define ADC_PWD_OFF	(1u)


#define ADC     ((adc_reg_t *)(T1_FSKDTMF_BASE + 0x200))

typedef struct {
        __IO uint32_t DAC_PWD_CTL;
}dac_reg_t;

/*dac_pwd_ctrl*/
#define DAC_PWD_ON	(0u)
#define DAC_PWD_OFF	(1u)

#define DAC     ((dac_reg_t *)(T1_FSKDTMF_BASE + 0x400))


typedef struct {
        __IO uint32_t RXA_PWD_CTL;
        __IO uint32_t RXA_BYP_CTL;
        __IO uint32_t RXA_GAIN_CTL;
}rxa_reg_t;

/*rx_pwd_ctrl*/
#define PWD_AMP_RX_ON			(~(1u<<0))
#define PWD_AMP_RX_OFF			(1u)
#define PWD_LPF_RX_ON			(~(1u<<1))
#define PWD_LPF_RX_OFF			(1u<<1)	
#define PWD_PGA_RX_ON			(~(1u<<2))
#define PWD_PGA_RX_OFF			(1u<<2)



/*rx_byp_ctrl*/
#define BYP_AMP_RX_ON			(1u)
#define BYP_AMP_RX_OFF			(~(1u<<0))
#define BYP_LPF_RX_ON			(1u<<1)
#define BYP_LPF_RX_OFF			(~(1u<<1))
#define BYP_PGA_RX_ON			(1u<<2)
#define BYP_PGA_RX_OFF			(~(1u<<2))


#define RXA     ((rxa_reg_t *)(T1_FSKDTMF_BASE + 0x600))

typedef struct {
        __IO uint32_t TXA_PWD_CTL;
        __IO uint32_t TXA_BYP_CTL;
        __IO uint32_t TXA_GAIN_CTL;
}txa_reg_t;

/*tx_pwd_ctrl*/
#define PWD_AMP_TX_ON			(~(1u<<0))
#define PWD_AMP_TX_OFF			(1u)
#define PWD_LPF_TX_ON			(~(1u<<1))
#define PWD_LPF_TX_OFF			(1u<<1)	
#define PWD_PGA_TX_ON			(~(1u<<2))
#define PWD_PGA_TX_OFF			(1u<<2)


/*tx_byp_ctrl*/
#define BYP_AMP_TX_ON			(1u)
#define BYP_AMP_TX_OFF			(~(1u<<0))
#define BYP_LPF_TX_ON			(1u<<1)
#define BYP_LPF_TX_OFF			(~(1u<<1))
#define BYP_PGA_TX_ON			(1u<<2)
#define BYP_PGA_TX_OFF			(~(1u<<2))


#define TXA     ((txa_reg_t *)(T1_FSKDTMF_BASE + 0x800))

typedef struct {
        __IO uint32_t REF_PWD_CTL;
        __IO uint32_t TS_CTL;
}ana_reg_t;

/* REF_PWD_CTL */
#define REF_PWD_ON	(0)
#define REF_PWD_OFF	(1)

#define ANA     ((ana_reg_t *)(T1_FSKDTMF_BASE + 0xA00))

#endif /* T1_FSK_H_ */

